This invention relates to electrical circuitry. More particularly, it is concerned with logic circuits having different logic levels and with interface arrangements between logic circuits having different logic levels.
Two widely used, well-known logic systems are ECL (emitter coupled logic) and CMOS (complementary metal oxide semiconductor) logic systems. The logic levels for ECL logic are -1.6 volt and -0.8 volt and for CMOS the logic levels are 0 volts and +5 volts. The threshold voltage for CMOS logic, that is the voltage at which a CMOS logic circuit triggers from one operating state to another, is +2.5 volts. Since this voltage is outside the operating range of ECL logic, CMOS logic circuitry is not directly compatible with ECL circuitry.
The circuit diagram of FIG. 1 illustrates the conventional technique heretofore employed to couple ECL logic circuitry to CMOS logic circuitry. An array of CMOS circuitry is indicated by the dashed line 10 in FIG. 1. The CMOS logic consists of an array of inverter circuits each including a P-type MOS transistor and its complement, an N-type MOS transistor, connected in series between +5 volts and ground. The gates of each pair are connected together and an output is taken from their common juncture. As is well-known, the output of each inverter stage is the inversion of its input. In order to change the logic levels from the ECL logic levels of -1.6 volts and -0.8 volts so as to accommodate the 0 and -5 volt logic levels of CMOS logic a conventional ECL/MOS translator 11 is connected at the input of the CMOS circuitry 10. At the output of CMOS circuitry an MOS/ECL translator 12 converts the 0/+5 volt CMOS logic levels to the -1.6/-0.8 volt ECL logic levels. In addition to requiring the +5 volt power supply used with the MOS circuitry, the translators also require -5 volts. Furthermore the translators consume physical space and consume power. They also introduce delay and power distortion.